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features description applications dac5571 slas405a ? december 2003 ? revised august 2005 +2.7 v to +5.5 v, i 2 c interface, voltage output, 8-bit digital-to-analog converter micropower operation: 125 a @ 3 v the dac5571 is a low-power, single-channel, 8-bit fast update rate: 188 ksps buffered voltage output dac. its on-chip precision output amplifier allows rail-to-rail output swing to be power-on reset to zero achieved. the dac5571 utilizes an i 2 c-compatible, +2.7-v to +5.5-v power supply two-wire serial interface that operates at clock rates specified monotonic by design up to 3.4 mbps with address support of up to two i 2 c? interface up to 3.4 mbps dac5571s on the same data bus. on-chip output buffer amplifier, rail-to-rail the output voltage range of the dac is 0 v to v dd . operation the dac5571 incorporates a power-on-reset circuit double-buffered input register that ensures that the dac output powers up at zero address support for up to two dac5571s volts and remains there until a valid write to the device takes place. the dac5571 contains a small 6 lead sot 23 package power-down feature, accessed via the internal control operation from ?40 c to 105 c register, that reduces the current consumption of the device to 50 na at 5 v. the low-power consumption of this part in normal process control operation makes it ideally suited for portable battery data acquistion systems operated equipment. the power consumption is less closed-loop servo control than 0.7 mw at v dd = 5 v reducing to 1 w in pc peripherals power-down mode. portable instrumentation dac7571/6571/5571 are 12/10/8-bit, single-channel i 2 c dacs from the same family. dac7574/6574/5574 and dac7573/6573/5573 are 12/10/8-bit quad-channel i 2 c dacs. also see dac8571/8574 for single/quad-channel, 16-bit i 2 c dacs. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. i 2 c is a trademark of philips corporation. production data information is current as of publication date. copyright ? 2003?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com v d d scl a0 gnd output buffer power-down control logic resistor network ref (+) ref(?) 8-bitdac i 2 c control logic dac register power-on reset v o u t sda
pin configurations absolute maximum ratings (1) dac5571 slas405a ? december 2003 ? revised august 2005 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information package specified tem- package ordering num- product package desig- transport media perature range marking ber nator dac5571idbvt 250-piece small tape and reel dac5571 sot23-6 dbv ?40c to +105c d571 DAC5571IDBVR 3000-piece tape and reel pin description (sot23-6) pin name description 1 v out analog output voltage from dac ground reference point for all 2 gnd circuitry 3 v dd analog voltage supply input 4 sda serial data input 5 scl serial clock input 6 a0 device address select lot year (3 = 2003); m onth (1?9 = jan?sep; a=oct, trace b=nov, c=dec); ll? random code generated code: when assembly is requested units v dd to gnd ? 0.3 v to +6 v digital input voltage to gnd ?0.3 v to +v dd +0.3 v v out to gnd ? 0.3 v to +v dd +0.3 v operating temperature range ?40 c to +105 c storage temperature range ?65 c to +150 c junction temperature range (t j max) +150 c power dissipation (t j max - t a )r qja thermal impedance, r qja 240 c/w lead temperature, soldering vapor phase (60s) 215 c infrared (15s) 220 c (1) stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. 2 www .ti.com a0scl sda 65 4 12 3 v o u t gnd v d d d571 12 3 65 4 ymll (t op view) (bott om view) lot t race code
electrical characteristics dac5571 slas405a ? december 2003 ? revised august 2005 v dd = +2.7 v to +5.5 v; r l = 2 k w to gnd; c l = 200 pf to gnd; all specifications ?40c to +105c unless otherwise noted. dac5571 parameter conditions units min typ max static performance (1) resolution 8 bits relative accuracy 0.5 lsb differential nonlinearity assured monotonic by design 0.25 lsb zero code error 5 20 mv full-scale error all ones loaded to dac register -0.15 -1.25 % of fsr gain error 1.25 % of fsr zero code error drift 7 v/c gain temperature coefficient 3 ppm of fsr/ c output characteristics (2) output voltage range 0 v dd v 1/4 scale to 3/4 scale change (400 h to c00 h ) ; output voltage settling time 6 8 s r l = slew rate 1 v/s r l = 470 pf capacitive load stability r l = 2 k w 1000 pf code change glitch impulse 1 lsb change around major carry 20 nv-s digital feedthrough 0.5 nv-s dc output impedance 1 w v dd = +5 v 50 ma short-circuit current v dd = +3 v 20 ma coming out of power-down mode, v dd = +5 v 2.5 s power-up time coming out of power-down mode, v dd = +3 v 5 s logic inputs (3) input current 1 a v in l, input low voltage v dd = +3 v 0.3v dd v v in h, input high voltage v dd = +5 v 0.7v dd v pin capacitance 3 pf power requirements v dd 2.7 5.5 v i dd (normal operation) dac active and excluding load current v dd = +3.6 v to +5.5 v v ih = v dd and v il = gnd 155 200 a v dd = +2.7 v to +3.6 v v ih = v dd and v il = gnd 125 160 a i dd (all power-down modes) v dd = +3.6 v to +5.5 v v ih = v dd and v il = gnd 0.2 1 a v dd = +2.7 v to +3.6 v v ih = v dd and v il = gnd 0.05 1 a power efficiency i out /i dd i load = 2 ma, v dd = +5 v 93 % (1) linearity calculated using a reduced code range of 3 to 253; output unloaded. (2) specified by design and characterization, not production tested. (3) specified by design and characterization, not production tested. 3 www .ti.com
timing characteristics dac5571 slas405a ? december 2003 ? revised august 2005 symbol parameter test conditions min typ max units f scl scl clock frequency standard mode 100 khz fast mode 400 khz high-speed mode, c b - 100 pf max 3.4 mhz high-speed mode, c b - 400 pf max 1.7 mhz t buf bus free time between a stop standard mode 4.7 s and start condition fast mode 1.3 s t hd ; t sta hold time (repeated) start standard mode 4.0 s condition fast mode 600 ns high-speed mode 160 ns t low low period of the scl clock standard mode 4.7 s fast mode 1.3 s high-speed mode, c b - 100 pf max 160 ns high-speed mode, c b - 400 pf max 320 ns t high high period of the scl clock standard mode 4.0 s fast mode 600 ns high-speed mode, c b - 100 pf max 60 ns high-speed mode, c b - 400 pf max 120 ns t su ; t sta setup time for a repeated standard mode 4.7 s start condition fast mode 600 ns high-speed mode 160 ns t su ; t dat data setup time standard mode 250 ns fast mode 100 ns high-speed mode 10 ns t hd ; t dat data hold time standard mode 0 3.45 s fast mode 0 0.9 s high-speed mode, c b - 100 pf max 0 70 ns high-speed mode, c b - 400 pf max 0 150 ns t rcl rise time of scl signal standard mode 1000 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b - 100 pf max 10 40 ns high-speed mode, c b - 400 pf max 20 80 ns t rcl1 rise time of scl signal after a standard mode 1000 ns repeated start condition and fast mode 20 + 0.1c b 300 ns after an acknowledge bit high-speed mode, c b - 100 pf max 10 80 ns high-speed mode, c b - 400 pf max 20 160 ns t fcl fall time of scl signal standard mode 300 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b - 100 pf max 10 40 ns high-speed mode, c b - 400 pf max 20 80 ns t rda rise time of sda signal standard mode 1000 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b - 100 pf max 10 80 ns high-speed mode, c b - 400 pf max 20 160 ns t fda fall time of sda signal standard mode 300 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b - 100 pf max 10 80 ns high-speed mode, c b - 400 pf max 20 160 ns 4 www .ti.com
typical characteristics: v dd = +5 v dac5571 slas405a ? december 2003 ? revised august 2005 timing characteristics (continued) symbol parameter test conditions min typ max units t su ; t sto setup time for stop condition standard mode 4.0 s fast mode 600 ns high-speed mode 160 ns c b capacitive load for sda and scl 400 pf t sp pulse width of spike suppressed fast mode 50 ns high-speed mode 10 ns v nh noise margin at the high level standard mode 0.2v dd v for each connected device fast mode (including hysteresis) high-speed mode v nl noise margin at the low level for standard mode 0.1v dd v each connected device fast mode (including hysteresis) high-speed mode at t a = +25c, +v dd = +5 v, unless otherwise noted. linearity error and linearity error and differential linearity error differential linearity error vs vs code (-40c) code (+25c ) figure 1. figure 2. linearity error and absolute error differential linearity error vs code (+105c) figure 3. figure 4. 5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 0 32 64 96 128 160 192 224 256 digital input code v d d = 5 v at 105 c le ? lsb dle ? lsb ?16 ?8 0 8 16 0 32 64 96 128 160 192 224 256 digital input code v d d = 5 v , t a = 25 c output error ? mv www .ti.com ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 0 32 64 96 128 160 192 224 256 digital input code v d d = 5 v at 25 c le ? lsb dle ? lsb ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 0 32 64 96 128 160 192 224 256 v d d = 5 v at ?40 c digital input code le ? lsb dle ? lsb
dac5571 slas405a ? december 2003 ? revised august 2005 typical characteristics: v dd = +5 v (continued) at t a = +25c, +v dd = +5 v, unless otherwise noted. zero-scale error full-scale error vs vs temperature temperature figure 5. figure 6. i dd histogram source and sink current capability figure 7. figure 8. supply current supply current vs vs code temperature figure 9. figure 10. 6 ?30 ?20 ?10 0 10 20 30 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 1 10 v d d = 5 v t ? temperature ? c zero-scale error ?30 ?20 ?10 0 10 20 30 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 1 10 v d d = 5 v full-scale error ? mv t ? temperature ? c 500 1000 1500 2000 2500 8090 1001 10 120130 140 150 160 170 180 190 200 0 v d d = 5 v i d d ? supply current ? a f ? frequency ? hz 0 v o u t ( v ) i s o u r c e / s i n k ( m a ) 5 1 0 1 5 54 3 2 1 0 d a c l o a d e d w i t h f f h d a c l o a d e d w i t h 0 0 h 0 100 200 300 400 500 0 2 32 64 96 128 160 192 224 252 255 code v d d = 5 v i dd a m ? supply current ? 0 50 100 150 200 250 300 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 1 10 v d d = 5 v ? supply current ? i dd a m t ? temperature ? c www .ti.com
dac5571 slas405a ? december 2003 ? revised august 2005 typical characteristics: v dd = +5 v (continued) at t a = +25c, +v dd = +5 v, unless otherwise noted. supply current power-down current vs vs supply voltage supply voltage figure 11. figure 12. supply current full-scale settling time vs logic input voltage figure 13. figure 14. 7 0 50 100 150 200 250 300 2.7 3.2 3.7 4.2 4.7 5.2 5.7 ? supply current ? i dd a m v d d ? supply v oltage ? v 2 . 7 i d d ( n a ) v d d ( v ) 3 . 2 3 . 7 4 . 2 4 . 7 5 . 2 5 . 7 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 + 2 5 c C 4 0 c + 1 0 5 c c l k ( 5 v / d i v ) v o u t ( 1 v / d i v ) t i m e ( 1 m s / d i v ) f u l l ? s c a l e c o d e c h a n g e 0 0 h t o f f h o u t p u t l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d w 0 i d d ( a ) v l o g i c ( v ) 1 2 3 4 5 2 5 0 0 2 0 0 0 1 5 0 0 1 0 0 0 5 0 0 0 www .ti.com
dac5571 slas405a ? december 2003 ? revised august 2005 typical characteristics: v dd = +5 v (continued) at t a = +25c, +v dd = +5 v, unless otherwise noted. full-scale settling time half-scale settling time figure 15. figure 16. half-scale settling time power-on reset to 0v figure 17. figure 18. exiting power down code change glitch (80 h loaded) figure 19. figure 20. 8 t i m e ( 1 s / d i v ) c l k ( 5 v / d i v ) v o u t ( 1 v / d i v ) f u l l ? s c a l e c o d e c h a n g e f f h t o 0 0 h o u t p u t l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d w m t i m e ( 1 s / d i v ) c l k ( 5 v / d i v ) v o u t ( 1 v / d i v ) h a l f ? s c a l e c o d e c h a n g e 4 0 h t o c 0 h o u t p u t l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d w m t i m e ( s / d i v ) c l k ( 5 v / d i v ) v o u t ( 1 v / d i v ) h a l f ? s c a l e c o d e c h a n g e c 0 h t o 4 0 h o u t p u t l o a d e d w i t h 2 k w a n d 2 0 0 p f t o g n d 1m 1 m t i m e ( 2 0 s / d i v ) l o a d e d w i t h 2 k t o v d d . v d d ( 1 v / d i v ) v o u t ( 1 v / d i v ) t i m e ( 0 . 5 s / d i v ) l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d . c o d e c h a n g e : 8 0 h t o 7 f h v o u t ( 2 0 m v / d i v ) w m t i m e ( 5 s / d i v ) c l k ( 5 v / d i v ) v o u t ( 1 v / d i v ) www .ti.com
typical characteristics: v dd = +2.7 v dac5571 slas405a ? december 2003 ? revised august 2005 at t a = +25c, +v dd = +2.7 v, unless otherwise noted. linearity error and linearity error and differential linearity error differential linearity error vs vs code (-40c) code (+25c) figure 21. figure 22. linearity error and absolute errors differential linearity error vs code (+105c) figure 23. figure 24. zero-scale error full-scale error vs vs temperature temperature figure 25. figure 26. 9 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 0 32 64 96 128 160 192 224 256 digital input code v d d = 2.7 v at ?40 c le ? lsb dle ? lsb ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 0 32 64 96 128 160 192 224 256 digital input code le ? lsb dle ? lsb v d d = 2.7 v at 25 c ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.25 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0.25 0 32 64 96 128 160 192 224 256 digital input code v d d = 2.7 v at 105 c le ? lsb dle ? lsb ?16 ?8 0 8 16 0 32 64 96 128 160 192 224 256 digital input code output error ? mv v d d = 2.7 v t a = 25 c ?50 ?30 ?10 10 30 50 70 90 1 10 ?30 ?20 ?10 0 10 20 30 v d d = 5 v v d d = 2.7 v full-scale error ? mv t ? temperature ? c ?30 ?20 ?10 0 10 20 30 ?50 ?30 ?10 10 30 50 70 90 1 10 v d d = 2.7 v zero-scalenerror ? mv t ? temperature ? c www .ti.com
dac5571 slas405a ? december 2003 ? revised august 2005 typical characteristics: v dd = +2.7 v (continued) at t a = +25c, +v dd = +2.7 v, unless otherwise noted. i dd histogram source and sink current capability figure 27. figure 28. supply current supply current vs vs code temperature figure 29. figure 30. supply current full scale settling time vs logic input voltage figure 31. figure 32. 10 0 500 1000 1500 2000 2500 8090 1001 10 120130 140 150 160 170 180 190 200 v d d = 2.7 v i d d ? supply current ? a f ? frequency ? hz 0 v o u t ( v ) i s o u r c e / s i n k ( m a ) 5 1 0 1 5 32 1 0 d a c l o a d e d w i t h f f h d a c l o a d e d w i t h 0 0 h v d d = + 3 v 0 100 200 300 400 500 0 2 32 64 96 128 160 192 224 252 255 v d d = 2.7 v code i dd a m ? supply current ? 0 50 100 150 200 250 300 ?50 ?30 ?10 10 30 50 70 90 1 10 v d d = 2.7 v ? supply current ? i dd a m t ? temperature ? c t i m e ( 1 s / d i v ) c l k ( 2 . 7 v / d i v ) v o u t ( 1 v / d i v ) f u l l ? s c a l e c o d e c h a n g e 0 0 h t o f f h o u t p u t l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d w m 0 i d d ( a ) v l o g i c ( v ) 1 2 3 4 5 2 5 0 0 2 0 0 0 1 5 0 0 1 0 0 0 5 0 0 0 www .ti.com
dac5571 slas405a ? december 2003 ? revised august 2005 typical characteristics: v dd = +2.7 v (continued) at t a = +25c, +v dd = +2.7 v, unless otherwise noted. full-scale settling time half-scale settling time figure 33. figure 34. half-scale settling time power-on reset 0 v figure 35. figure 36. exiting-power down (80 h loaded) code change glitch figure 37. figure 38. 11 t i m e ( 1 s / d i v ) c l k ( 2 . 7 v / d i v ) v o u t ( 1 v / d i v ) f u l l ? s c a l e c o d e c h a n g e f f h t o 0 0 h o u t p u t l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d w m t i m e ( 1 s / d i v ) c l k ( 2 . 7 v / d i v ) v o u t ( 1 v / d i v ) h a l f ? s c a l e c o d e c h a n g e 4 0 h t o c 0 h o u t p u t l o a d e d w i t h 2 w a n d 2 0 0 p f t o g n d k t i m e ( 1 s / d i v ) c l k ( 2 . 7 v / d i v ) v o u t ( 1 v / d i v ) h a l f ? s c a l e c o d e c h a n g e c 0 h t o 4 0 h o u t p u t l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d w m p o w e r - o n r e s e t t o 0 v t i m e ( 2 0 s / d i v ) t i m e ( 0 . 5 s / d i v ) l o a d e d w i t h 2 k a n d 2 0 0 p f t o g n d . c o d e c h a n g e : 8 0 h t o 7 f h . v o u t ( 2 0 m v / d i v ) h t i m e ( 5 s / d i v ) c l k ( 2 . 7 v / d i v ) v o u t ( 1 v / d i v ) www .ti.com
theory of operation d/a section resistor string output amplifier i 2 c interface dac5571 slas405a ? december 2003 ? revised august 2005 the architecture of the dac5571 consists of a string dac followed by an output buffer amplifier. figure 39 shows a block diagram of the dac architecture. figure 39. r-string dac architecture the input coding to the dac5571 is unsigned binary, which gives the ideal output voltage as: where d = decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 255. the resistor string section is shown in figure 40 . it is basically a divide-by-2 resistor, followed by a string of resistors, each of value r. the code loaded into the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. because the architecture consists of a string of resistors, it is specified monotonic. figure 40. resistor string the output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it is capable of driving a load of 2 k w in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. the slew rate is 1 v/s with a half-scale settling time of 7 s with the output unloaded. i 2 c is a two-wire serial interface developed by philips semiconductor (see i 2 c-bus specification, version 2.1, january 2000). the bus consists of a data line (sda) and a clock line (scl) with pullup structures. when the bus is idle, both sda and scl lines are pulled high. all the i 2 c compatible devices connect to the i 2 c bus through open drain i/o pins, sda and scl. a master device, usually a microcontroller or a digital signal processor, controls the bus. the master is responsible for generating the scl signal and device addresses. the master also generates specific conditions that indicate the start and stop of data transfer. a slave device receives and/or transmits data on the bus under control of the master device. the dac5571 works as a slave and supports the following data transfer modes, as defined in the i 2 c-bus 12 ref (+)ref ( - ) resistor string outputamplifier v o u t gnd v d d dac register v o u t v d d t o output amplifier r r r r gnd www .ti.com
f/s-mode protocol hs-mode protocol dac5571 slas405a ? december 2003 ? revised august 2005 theory of operation (continued) specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 mbps). the data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as f/s-mode in this document. the protocol for high-speed mode is different from the f/s-mode, and it is referred to as hs-mode. the dac5571 supports 7-bit addressing; 10-bit addressing and general call address are not supported. the master initiates data transfer by generating a start condition. the start condition is when a high-to-low transition occurs on the sda line while scl is high, as shown in figure 41 . all i 2 c-compatible devices should recognize a start condition. the master then generates the scl pulses and transmits the 7-bit address and the read/write direction bit r/ w on the sda line. during all transmissions, the master ensures that data is valid. a valid data condition requires the sda line to be stable during the entire high period of the clock pulse (see figure 42 ). all devices recognize the address sent by the master and compare it to their internal fixed addresses. only the slave device with a matching address generates an acknowledge (see figure 43 ) by pulling the sda line low during the entire high period of the ninth scl cycle. on detecting this acknowledge, the master knows that a communication link with a slave has been established. the master generates further scl cycles to either transmit data to the slave (r/ w bit 1) or receive data from the slave (r/ w bit 0). in either case, the receiver needs to acknowledge the data sent by the transmitter. so an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. to signal the end of the data transfer, the master generates a stop condition by pulling the sda line from low to high while the scl line is high (see figure 41 ). this releases the bus and stops the communication link with the addressed slave. all i 2 c compatible devices must recognize the stop condition. on the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. when the bus is idle, both sda and scl lines are pulled high by the pullup devices. the master generates a start condition followed by a valid serial byte containing hs master code 00001xxx. this transmission is made in f/s-mode at no more than 400 kbps. no device is allowed to acknowledge the hs master code, but all devices must recognize it and switch their internal setting to support 3.4 mbps operation. the master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). after this repeated start condition, the protocol is the same as f/s-mode, except that transmission speeds up to 3.4 mbps are allowed. a stop condition ends the hs-mode and switches all the internal settings of the slave devices to support the f/s-mode. instead of using a stop condition, repeated start conditions should be used to secure the bus in hs-mode. figure 41. start and stop conditions 13 start condition sda stop condition sda scl s p scl www .ti.com
dac5571 slas405a ? december 2003 ? revised august 2005 theory of operation (continued) figure 42. bit transfer on the i 2 c bus figure 43. acknowledge on the i 2 c bus figure 44. bus protocol 14 www .ti.com change of data allowed data line stable; data v alid sda scl not acknowledge acknowledge 1 2 8 9 clock pulse for acknowledgement s st art condition data output by t ransmitter data output by receiver scl from master recognize st art or repea ted st art condition recognize st op or repea ted st art condition generate acknowledge signal acknowledgementsignal from slave sda scl msb p srsr or p s or sr st art or repeated st art condition st op or repeated st art condition clock line held low while interrupts are serviced 1 2 7 8 9 ack 1 2 3 - 8 9 ack address r/w
dac5571 i 2 c update sequence dac5571 slas405a ? december 2003 ? revised august 2005 theory of operation (continued) the dac5571 requires a start condition, a valid i 2 c address, a control-msb byte, and an lsb byte for a single update. after the receipt of each byte, dac5571 acknowledges by pulling the sda line low during the high period of a single clock pulse. a valid i 2 c address selects the dac5571. the ctrl/msb byte sets the operational mode of the dac5571, and the four most significant bits. the dac5571 then receives the lsb byte containing four least significant data bits followed by four don't care bits. dac5571 performs an update on the falling edge of the acknowledge signal that follows the lsb byte. for the first update, dac5571 requires a start condition, a valid i 2 c address, a ctrl/msb byte, an lsb byte. for all consecutive updates, dac5571 needs a ctrl/msb byte, and an lsb byte. using the i 2 c high-speed mode (f scl = 3.4 mhz), the clock running at 3.4 mhz, each 8-bit dac update other than the first update can be done within 18 clock cycles (ctrl/msb byte, acknowledge signal, lsb byte, acknowledge signal), at 188.88 ksps. using the fast mode (f scl = 400 khz), clock running at 400 khz, maximum dac update rate is limited to 22.22 ksps. once a stop condition is received, dac5571 releases the i 2 c bus and awaits a new start condition. address byte msb lsb 1 0 0 1 1 0 a0 0 the address byte is the first byte received following the start condition from the master device. the first six bits (msbs) of the address are factory preset to 100110. the next bit of the address is the device select bit a0. the a0 address input can be connected to v dd or digital gnd, or can be actively driven by ttl/cmos logic levels. the device address is set by the state of this pin during the power-up sequence of the dac5571. up to two devices (dac5571) can be connected to the same i 2 c-bus without requiring additional glue logic. broadcast address byte msb lsb 1 0 0 1 0 0 0 0 broadcast addressing is also supported by dac5571. broadcast addressing can be used for synchronously updating or powering down multiple dac5571 devices. using the broadcast address, dac5571 responds regardless of the state of the address pin a0. control - most significant byte most significant byte ctrl/msb[7:0] consists of two zeros, two power-down bits, and four most significant bits of 8-bit unsigned binary d/a conversion data. least significant byte least significant byte lsb[7:0] consists of the four least significant bits of the 8-bit unsigned binary d/a conversion data, followed by four don't care bits. dac5571 updates at the falling edge of the acknowledge signal that follows the lsb[0] bit. 15 www .ti.com
dac5571 slas405a ? december 2003 ? revised august 2005 figure 45. master transmitter addressing dac5571 as a slave receiver with a 7-bit address 16 www .ti.com sla ve address r/w a ctrl/ms-byte a ls-byte a/a p o0o (write) data t ransferred (n* w ords + acknowledge) w ord = 16 bit from master to dac5571 from dac5571 to master a = acknowledge (sda low) a = not acknowledge (sda high) s = st art condition sr = repeated st art condition p = st op condition dac5571 i 2 c-sla ve address: 1 0 0 1 1 0 a0 r/w msb lsb factory preset a0 = i 2 c address pin standard- and fast-mode: s hs-master code r/w a ctrl/ms-byte a ls-byte a/a p o0o (write) data t ransferred (n* w ords + acknowledge) w ord = 16 bit high-speed mode (hs mode): s a sr slave address hs mode continues f/s-mode hs mode f/s mode sr slave address 0 0 0 0 1 x x r/w msb lsb hs-mode master code: 0 0 pd1 pd0 d7 d6 d5 d4 msb lsb ctrl/ms-byte: d3 d2 d1 d0 x x x x msb lsb ls-byte: d7 ? d0 = data bits '0' = w rite to dac5571
power-on reset power-down modes current consumption driving resistive and capacitive loads dac5571 slas405a ? december 2003 ? revised august 2005 the dac5571 contains a power-on reset circuit that controls the output voltage during power up. on power up, the dac register is filled with zeros and the output voltage is 0 v. it remains at a zero-code output until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the dac output while it is in the process of powering up. the dac5571 contains four separate modes of operation. these modes are programmable via two bits (pd1 and pd0). table 1 shows how the state of these bits correspond to the mode of operation. table 1. modes of operation for the dac5571 pd1 pd0 operating mode 0 0 normal operation 0 1 1k w to agnd, pwd 1 0 100 k w to agnd, pwd 1 1 high impedance, pwd when both bits are set to zero, the device works normally with normal power consumption of 150 a at 5 v. however, for the three power-down modes, the supply current falls to 200 na at 5 v (50 na at 3 v). not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the device is known while in power-down mode. there are three different options: the output is connected internally to agnd through a 1-k w resistor, a 100-k w resistor, or it is left open-circuited (high impedance). the output stage is illustrated in figure 46 . figure 46. output stage during power down all linear circuitry is shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power down. the time required to exit power down is typically 2.5 s for av dd = 5 v and 5 s for av dd = 3 v. see the typical characteristics section for more information. the dac5571 typically consumes 150 a at v dd = 5 v and 120 a at v dd = 3 v. additional current consumption can occur due to the digital inputs if v ih << v dd . for most efficient power operation, cmos logic levels are recommended at the digital inputs to the dac. in power-down mode, typical current consumption is 200 na. the dac5571 output stage is capable of driving loads of up to 1000 pf while remaining stable. within the offset and gain error margins, the dac5571 can operate rail-to-rail when driving a capacitive load. when the outputs of the dac are driven to the positive rail under resistive loading, the pmos transistor of each class-ab output stage can enter into the linear region. when this occurs, the added ir voltage drop deteriorates the linearity performance of the dac. this may occur within approximately the top 20 mv of the dac's digital input-to-voltage output transfer characteristic. 17 www .ti.com resistor string dac power-down v o u t amplifier resistor network circuitry
output voltage stability applications using ref02 as a power supply for the dac5571 layout dac5571 slas405a ? december 2003 ? revised august 2005 the dac5571 exhibits excellent temperature stability of 5 ppm/ c typical output voltage drift over the specified temperature range of the device. this enables the output voltage to stay within a 25- v window for a 1 c ambient temperature change. combined with good dc noise performance and true 8-bit differential linearity, the dac5571 becomes a perfect choice for closed-loop control applications. due to the extremely low supply current required by the dac5571, a possible configuration is to use a ref02 +5-v precision voltage reference to supply the required voltage to the dac5571's supply input as well as the reference input, as shown in figure 47 . this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v. the ref02 outputs a steady supply voltage for the dac5571. if the ref02 is used, the current it needs to supply to the dac5571 is 140 a typical. when a dac output is loaded, the ref02 also needs to supply the current to the load. the total typical current required (with a 5-mw load on a given dac output) is: 140 a + (5 mw/5 v) = 1.14 ma. the load regulation of the ref02 is typically (0.005% v dd )/ma, which results in an error of 0.285 mv for the 1.14-ma current drawn from it. this corresponds to a 0.015 lsb error for a 0-v to 5-v output range. figure 47. ref02 as power supply to dac5571 a precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. the power applied to v dd should be well regulated and low noise. switching power supplies and dc/dc converters often has high-frequency glitches or spikes riding on the output voltage. in addition, digital components can create similar high-frequency spikes as their internal logic switches states. this noise can easily couple into the dac output voltage through various paths between the power connections and analog output. as with the gnd connection, v dd should be connected to a +5-v power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. in addition, the 1- f to 10- f and 0.1- f bypass capacitors are strongly recommended. in some situations, additional bypassing may be required, such as a 100- f electrolytic capacitor or even a pi filter made up of inductors and capacitors?all designed to essentially low-pass filter the +5-v supply, removing the high-frequency noise. 18 www .ti.com ref02 15 v 5 v 1.14 ma a0 scl sda i 2 c interface v o u t = 0 v to 5 v dac5571
package option addendum www.ti.com 22-oct-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) DAC5571IDBVR active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples DAC5571IDBVRg4 active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples dac5571idbvt active sot-23 dbv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples dac5571idbvtg4 active sot-23 dbv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DAC5571IDBVR sot-23 dbv 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 dac5571idbvt sot-23 dbv 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 package materials information www.ti.com 8-jul-2011 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DAC5571IDBVR sot-23 dbv 6 3000 180.0 180.0 18.0 dac5571idbvt sot-23 dbv 6 250 180.0 180.0 18.0 package materials information www.ti.com 8-jul-2011 pack materials-page 2

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